Zero instruction set computer

In computer science, Zero Instruction Set Computer (ZISC) refers to a computer architecture based on pure pattern matching and absence of (micro-)instructions in the classical sense.

The ZISC acronym alludes to the previously developed RISC (Reduced Instruction Set Computer) technology.


ZISC is a technology based on ideas from artificial neural networks and massively hardwired parallel processing. This concept was invented by Guy Paillet.[1]

Zero instruction set computers should not be confused with analogue computers. Analogue computers do not have the ability to carry out instructions.

Design features

The ZISC architecture alleviates the memory bottleneck by blending the pattern memory with the pattern learning and recognition logic.

The main innovation was finding a way to solve the "winner takes all problem" and allows a constant learning/recognition time, regardless of the number of processing elements (e.g. neurons) connected in parallel.

The first ZISC35 with 36 neurons was released in 1993 and the ZISC78 in 2000, both by IBM, which discontinued their manufacturing in 2001.

In August 2007, the CM1K (CogniMem 1,024 neurons) was introduced by CogniMem Ltd. CM1K was designed by Anne Menendez and Guy Paillet.

Practical uses of ZISC/CogniMem technology focus on pattern recognition, information retrieval (data mining), security and similar tasks.


ZISC genesis and succession

See also

External links

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