SuperSPARC
|
The SuperSPARC microprocessor | |
| Produced | From 1992 to 1995 |
|---|---|
| Designed by | Sun Microsystems |
| Max. CPU clock rate | 33 MHz to 90 MHz |
| Instruction set | SPARC V8 |
| Cores | 1 |
The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contained 3.1 million transistors. It was fabricated by Texas Instruments (TI) at Miho, Japan in a 0.8 micrometre triple-metal[1] BiCMOS process.[2]
There were two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 80 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E.
The SuperSPARC-II was replaced in 1995 by the 64-bit UltraSPARC, an implementation of the 64-bit SPARC V9 ISA.
Models
| Name (codename) | Model | Frequency (MHz) | Arch. version | Year | Total threads[3] | Process (µm) | Transistors (millions) | Die size (mm²) | IO Pins | Power (W) | Voltage (V) | L1 Dcache (k) | L1 Icache (k) | L2 Cache (k) | L3 Cache (k) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SuperSPARC I (Viking) | TI TMX390Z50 / Sun STP1020 | 33–60 | V8 | 1992 | 1×1=1 | 0.8 | 3.1 | -- | 293 | 14.3 | 5 | 16 | 20 | 0-2048 | none |
| SuperSPARC II (Voyager) | Sun STP1021 | 75–90 | V8 | 1994 | 1×1=1 | 0.8 | 3.1 | 299 | -- | 16 | -- | 16 | 20 | 1024-2048 | none |
SuperSPARC (Viking)
- SM20: 1 CPU, no L2-Cache, 33 MHz Bus: 33 MHz
- SM21: 1 CPU, 1 MB L2-Cache, 33 MHz Bus: 33 MHz
- SM30: 1 CPU, no L2-Cache, 36 MHz Bus: 36 MHz
- SM40: 1 CPU, no L2-Cache, 40 MHz Bus: 40 MHz
- SM41: 1 CPU, 1 MB L2-Cache, 40 MHz Bus: 40 MHz
- SM50: 1 CPU, no L2-Cache, 50 MHz Bus: 50 MHz
- SM51: 1 CPU, 1 MB L2-Cache, 50 MHz Bus: 40 MHz
- SM51-2: 1 CPU, 2 MB L2-Cache, 50 MHz Bus: 40 MHz
- SM52: 2 CPU, 1 MB L2-Cache, 45 MHz Bus: 40 MHz
- SM52X: 2 CPU, 1 MB L2-Cache, 50 MHz Bus: 40 MHz
- SM61: 1 CPU, 1 MB L2-Cache, 60 MHz Bus: 50 MHz
- SM61-2: 1 CPU, 2 MB L2-Cache, 60 MHz Bus: 50 MHz
SuperSPARC II (Voyager)
- SM71: 1 CPU, 1 MB L2-Cache, 75 MHz Bus: 50 MHz
- SM81: 1 CPU, 1 MB L2-Cache, 85 MHz Bus: 50 MHz
- SM81-2: 1 CPU, 2 MB L2-Cache, 85 MHz Bus: 50 MHz
- SM91-2: 1 CPU, 2 MB L2-Cache, 90 MHz Bus: 50 MHz
- Die photos
TI SuperSPARC I
Sun SuperSPARC II
References
- ↑ SuperSPARC Microprocessor Fact Sheet
- ↑ Testability features of the SuperSPARC microprocessor. Sun 1993
- ↑ Threads per core × number of cores
- "TI SuperSPARC for Sun Station 3 in production". (11 May 1992). Electronic News.
- DeTar, Jim (10 October 1994). "Sun sets SuperSPARC-II as UltraSPARC V9 bridge". Electronic News.