MCST-R1000
|
MCST R1000 FPGA prototype | |
| Produced | 2010[1] |
|---|---|
| Designed by | MCST |
| Common manufacturer(s) | |
| Max. CPU clock rate | 750 MHz to 1 GHz |
| FSB speeds | 2 Gbps |
| Min. feature size | 100 mm² |
| Instruction set | SPARC V9 |
| Cores | 4 |
| L1 cache | 48 KB |
| L2 cache | 2 MB |
| Predecessor | MCST-R500S |
| Application | Embedded |
| Package(s) | |
The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.[2]
During development this microprocessor was designated as MCST-4R.[1]
MCST R1000 Highlights
- implements the SPARC V9 instruction set architecture (ISA)
- quad-core
- core specifications:
- in-order, dual-issue superscalar
- 7-stage integer pipeline
- 9-stage floating-point pipeline
- VIS extensions 1 and 2
- Multiply–accumulate unit
- 16 KB L1 instruction cache (parity protection)
- 32 KB L1 data cache (parity protection)
- size 7.6 mm2
- shared 2MB L2 cache (ECC protection)
- integrated memory controller
- integrated ccNUMA controller
- 1 GHz clock rate
- 90 nm process
- die size 128 mm2
- ~150 million transistors
- power consumption 15W
 MCST R1000 core |  MCST R1000 pipeline |  MCST R1000 diagram |  ccNUMA multiprocessor system with four MCST R1000 microprocessors |
References
- 1 2 "Участие ЗАО «МЦСТ» и ОАО «ИНЭУМ им.И.С.Брука» в международной выставке "ChipExpo – 2011" (итоги участия)", Новости (in Russian), MCST, retrieved 2011-12-06
- ↑ Система на кристалле "МЦСТ-4R" (in Russian), MCST, retrieved 2011-11-18
This article is issued from Wikipedia - version of the 5/22/2015. The text is available under the Creative Commons Attribution/Share Alike but additional terms may apply for the media files.