Bus contention

Bus contention, in computer design, is an undesirable state of the bus in which more than one device on the bus attempts to place values on the bus at the same time. Most bus architectures require their devices follow an arbitration protocol carefully designed to make the likelihood of contention negligible.[1] However, when devices on the bus have logic errors, manufacturing defects or are driven beyond their design speeds, arbitration may break down and contention may result. Contention may also arise on systems which have a programmable memory mapping and when illegal values are written to the registers controlling the mapping.

Contention can lead to erroneous operation, and in unusual cases, damage to the hardware—such as fusing of the bus wiring.

Bus contention is sometimes countered by buffering the output of memory-mapped devices. However, it has been noted that high impedance from one device will still interfere with the bus values of other devices. Currently, no standard solution exists for data-bus contention between memory devices, such as EEPROM and SRAM.


  1. Tanenbaum, Andrew (1990), Structured Computer Organization (3rd ed.), Prentice Hall, pp. 121–124, ISBN 0-13-852872-1.
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